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- LDO design issue - no load condition | Forum for Electronics
Hi I am working on a LDO design that requires a rather large PMOS pass transistor due to the specified max current I have issues with pulling the pass transistor gate high enough at no load conditions to avoid the output voltage creeping upwards due to leakage in the pass transistor In
- Comparison of LDO and level shifter | Forum for Electronics
Re: LDO vs Level shifter The main benefit of an LDO over a buck converter is lower noise However, the efficiency is worse especially for large voltage drops 12 V to 3 3 V implies an efficiency of 28% for the LDO, vs 80-90% for the buck
- LDO with NMOS as pass transistor. . - Forum for Electronics
The advantages of a NMOS transistor (source follower output) in LDO is that the output capacitance can be very small (few pF) and because of the inherent low impedance at the output, the output need not be a dominant pole In PMOS pass transistor LDO's, the output has to be generally a dominant pole thus needing a large load cap for being stable
- behavioral modelling for LDO | Forum for . . . - Forum for Electronics
verilog-a ldo Thanx sunking and sixth, now to start with my design, i have nmos and pmos devices categorized as Logic , MM and RF can someone explain what exactly Logic, MM and RF devices means are they modelled differently?? cant i use an RF or logic device to design an LDO any document regarding this would be very helpful thanx in advance
- How to properly do AC open loop LDO simulation?
ac analysis of ldo I also confused it, sometimes, I use the AC source with ac=1V to break the loop sometime, I use the resistor with AC=1G , and a cap=1F and sometime, I use the ind=1G and a cap =1F the only diff thing I thought is the phase of it different But offten, the gain plot is also diff
- How to measure psrr of LDO? - Forum for Electronics
ldo psrr PSRR shows how the LDO output varies in accordance with power supply noise You will need either HSpice or Cadence to run your simulation For Cadence: Place a vdc source at the power supply net Set ac=1 for this along with its DC value Run AC analysis Use the direct plot drop down menu (Results) and click on AC dB20
- [SOLVED] Input Power source selection for ESP32(LDO)
Two LDO´s output connected, while there is logic to enable disable the according LDO accoring input situation For sure you need to chose a suitable LDO Yes, LDO even if you use a single LDO it will have some voltage drop You need to care about For the peak load current you expect *** There are "ideal diodes" Check them out ***
- How to compensate my LDO - Forum for Electronics
Re: LDO compensation If the LDO output comes to a pin , then large external capacitor use is possible and hence the output is made as a dominant pole Such architecture has PMOS output transistor (high output impedance , Rds) and worst case for stability at high load currents ( low output impedance , 1 lambda*Id)
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